ATmega649 Atmel Corporation, ATmega649 Datasheet - Page 263
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ATmega649
Manufacturer Part Number
ATmega649
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega649-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega649-16MU
Manufacturer:
Atmel
Quantity:
135
Part Number:
ATmega6490-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Company:
Part Number:
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Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
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Manufacturer:
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1 500
Company:
Part Number:
ATmega6490A-AU
Manufacturer:
Atmel
Quantity:
1 250
Company:
Part Number:
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Manufacturer:
Maxim
Quantity:
43
2552K–AVR–04/11
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 25-6.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Step
1
2
3
4
5
6
7
8
9
10
11
Table
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned
out to be 0
Verify the
COMP bit
scanned
out to be 1
25-6. Only the DAC and port pin values of the Scan Chain are shown. The column
Algorithm for Using the ADC
The lower limit is:
The upper limit is:
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 25-5
1024 1.5V 0,95 5V
MUXEN
1024 1.5V 1.05 5V
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
⋅
⋅
are used unless other values are given in the algo-
ATmega329/3290/649/6490
HOLD
⋅
⋅
1
0
1
1
1
1
0
1
1
1
1
⁄
⁄
PRECH
1
1
1
1
0
1
1
1
1
0
1
=
=
291
323
PA3.
Data
CC
=
=
0
0
0
0
0
0
0
0
0
0
0
.
0x123
0x143
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Pull-
up_
Enable
0
0
0
0
0
0
0
0
0
0
0
263