ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 160

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.9.2
17.9.3
17.9.4
17.9.5
8160C–AVR–07/09
TCNT2 – Timer/Counter Register
OCR2 – Output Compare Register
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2 pin.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter2 occurs, for example, when the OCF2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, for example, when the TOV2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
Bit
0x24 (0x44)
Read/Write
Initial Value
Bit
0x23 (0x43)
Read/Write
Initial Value
Bit
0x37 (0x57)
Read/Write
Initial Value
Bit
0x36 (0x56)
Read/Write
Initial Value
OCIE2
OCF2
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
TOIE2
TOV2
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
TICIE1
R/W
ICF1
R/W
R/W
R/W
5
0
5
0
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
TCNT2[7:0]
OCR2[7:0]
OCIE1B
OCF1B
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
TOIE1
TOV1
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE0
OCF0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
ATmega64A
TOIE0
TOV0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TCNT2
TIMSK
OCR2
TIFR
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