ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 314

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 27-15. SPI Serial Programming Instruction Set (Continued)
Note:
27.8.4
27.9
27.9.1
8160C–AVR–07/09
Instruction
Read Extendend Fuse
Bits
Read Fuse High Bits
Read Calibration Byte
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Programming Via the JTAG Interface
SPI Serial Programming Characteristics
Programming Specific JTAG Instructions
For characteristics of the SPI module, see
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.
Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in running mode while still allowing In-System
Programming via the JTAG interface. Note that this technique can not be used when using the
JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedi-
cated for this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.
The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
0101 0000
0101 1000
0011 1000
Byte 1
0000 1000
0000 1000
00xx xxxx
Byte 2
Instruction Format
Figure
xxxx xxxx
xxxx xxxx
0000 00bb
Byte 3
27-12.
“SPI Timing Characteristics” on page
oooo oooo
oooo oooo
oooo oooo
Byte4
Operation
Read Extended Fuse bits. “0” =
pro-grammed, “1” =
unprogrammed. See
page 297
Read Fuse high bits. “0” = pro-
grammed, “1” = unprogrammed.
See
details.
Read Calibration Byte o at address
b.
Table 27-4 on page 297
for details.
ATmega64A
333.
Table 27-5 on
for
314