ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 177

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.3.1
20.3.2
8160C–AVR–07/09
Internal Clock Generation – The Baud Rate Generator
Double Speed Operation (U2Xn)
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register n (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator
output is used directly by the receiver’s clock and data recovery units. However, the recovery
units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCK bits.
Table 20-1
ing the UBRRn value for each mode of operation using an internally generated clock source.
Table 20-1.
Note:
Some examples of UBRRn values for some system clock frequencies are found in
page 192
The transfer rate can be doubled by setting the U2Xn bit in UCSRnB. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
OSC
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
), is loaded with the UBRRn value each time the counter has counted down to zero or when
xcko
fosc
BAUD
f
UBRR
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps).
to
contains equations for calculating the baud rate (in bits per second) and for calculat-
Table 20-7 on page
Equations for Calculating Baud Rate Register Setting
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0 - 4095)
BAUD
BAUD
BAUD
Equation for Calculating
195.
=
=
=
Baud Rate
----------------------------------------- -
16 UBRR
-------------------------------------- -
2 UBRR
-------------------------------------- -
8 UBRRn
(
(
(
f
f
f
OSC
OSC
OSC
(1)
+
+
+
1n
Figure
OSC
1n
1
)
)
)
/(UBRRn+1)). The transmitter divides the
20-2.
UBRRn
UBRRn
UBRRn
Equation for Calculating
UBRR Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
ATmega64A
OSC
OSC
OSC
–
–
–
Table 20-4 on
177