ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 264

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.5.2
8160C–AVR–07/09
Boundary-scan and the Two-wire Interface
Figure 25-4. General Port Pin Schematic Diagram
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in
Note:
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
See Boundary-scan Description
for Details!
Pxn
support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
drive contention.
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
Figure 25-9
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
PUExn
is attached to the TWIEN signal.
SLEEP
OCxn
ODxn
SYNCHRONIZER
WDx:
RDx:
WPx:
RRx:
RPx:
CLK
D
L
Q
Q
Figure
I/O
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
25-5, the TWIEN signal enables
Q
Q
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
ATmega64A
CLK
PUD
WDx
RDx
WPx
RPx
RRx
I/O
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