ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 218

• Manufacturer Part Number: ATmega64M1
• Manufacturer: Atmel Corporation

Specifications of ATmega64M1

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.6.3
218
ATmega16M1/32M1/64M1
LINENIR – LIN Enable Interrupt Register
• Bit 2 - LIDOK: Identifier Interrupt
• Bit 1 - LTXOK: Transmit Performed Interrupt
• Bit 0 - LRXOK: Receive Performed Interrupt
• Bits 7:4 - Res: Reserved
• Bit 3 - LENERR: Enable Error Interrupt
• Bit 2 - LENIDOK: Enable Identifier Interrupt
Bit
Read/Write
Initial Value
resets all LINERR bits.
written to zero when LINENIR is written.
– 0 = No identifier
– 1 = Slave task: Identifier present, master task: Tx Header complete
– 0 = No Tx
– 1 = Tx Response complete
– 0 = No Rx
– 1 = Rx Response complete
– 0 = Error interrupt masked
– 1 = Error interrupt enabled
– 0 = Identifier interrupt masked
– 1 = Identifier interrupt enabled
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
In UART mode, this bit is also cleared by reading LINDAT.
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
These bits are reserved for future use. For compatibility with future devices, they must be
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
LENERR
R/W
3
0
LENIDOK
R/W
2
0
LENTXOK
R/W
1
0
LENRXOK
R/W
0
0
8209D–AVR–11/10
LINENIR