ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 65
ATmega64M1
Manufacturer Part Number
ATmega64M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega64M1
Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega64M1-15MD
Manufacturer:
ATMEL
Quantity:
700
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13.2
13.2.1
8209D–AVR–11/10
Ports as General Digital I/O
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 13-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin.
The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Pxn
SLEEP, and PUD are common to all ports
83, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
SLEEP: SLEEP CONTROL
clk
PUD: PULLUP DISABLE
I/O
: I/O CLOCK
(1)
SLEEP
ATmega16M1/32M1/64M1
SYNCHRONIZER
D
L
WDx: WRITE DDRx
RDx: READ DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
WPx: WRITE PINx REGISTER
Q
Q
D
PINxn
Q
Q
Figure 13-2
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
shows a func-
PUD
clk
WDx
RDx
RPx
1
0
I/O
“Register
WPx
WRx
I/O
,
65
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