ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 15

• Manufacturer Part Number: ATtiny13
• Manufacturer: Atmel Corporation

Specifications of ATtiny13

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5. Memories
5.1
5.2
2535J–AVR–08/10
In-System Reprogrammable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATtiny13. The AVR architecture has two
main memory spaces, the Data memory and the Program memory space. In addition, the
ATtiny13 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13 Pro-
gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations.
“Memory Programming” on page 102
loading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 5-1.
Figure 5-2 on page 16
The lower 160 Data memory locations address both the Register File, the I/O memory and the
internal data SRAM. The first 32 locations address the Register File, the next 64 locations the
standard I/O memory, and the last 64 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
12.
Program Memory Map
shows how the ATtiny13 SRAM Memory is organized.
Program Memory
contains a detailed description on Flash data serial down-
0x01FF
0x0000
“Instruction Execution Tim-
15