ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 46
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ATtiny13
Manufacturer Part Number
ATtiny13
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny13
Flash (kbytes)
1 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.06
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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9.3
9.3.1
9.3.2
46
Register Description
ATtiny13
MCUCR – MCU Control Register
GIMSK – General Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 9-2.
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt
Vector. PCINT5..0 pins are enabled individually by the PCMSK Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00
R
7
–
0
R
7
–
0
0
1
0
1
Table 9-2 on page
PUD
R/W
INT0
R/W
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
6
0
6
0
R/W
PCIE
R/W
SE
5
0
5
0
SM1
R/W
4
0
R
46. The value on the INT0 pin is sampled before
4
–
0
SM0
R/W
3
0
R
3
–
0
R
2
–
0
R
2
–
0
ISC01
R/W
1
0
R
1
–
0
ISC00
R/W
0
0
R
0
–
0
2535J–AVR–08/10
MCUCR
GIMSK