ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 16
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ATtiny13
Manufacturer Part Number
ATtiny13
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny13
Flash (kbytes)
1 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.06
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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5.2.1
5.3
5.3.1
16
EEPROM Data Memory
ATtiny13
Data Memory Access Times
EEPROM Read/Write Access
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data
SRAM in the ATtiny13 are all accessible through all these addressing modes. The Register File
is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register. For a detailed description of Serial data downloading to the
EEPROM, see
The EEPROM Access Registers are accessible in the I/O space.
Data Memory Map
On-chip Data SRAM Access Cycles
“General Purpose Register File” on page
page
Address
clk
Data
Data
WR
CPU
RD
105.
Compute Address
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
T1
(64 x 8)
Memory Access Instruction
Address valid
0x009F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
CPU
T2
cycles as described in
10.
Next Instruction
T3
Figure
2535J–AVR–08/10
5-3.