ATtiny24A Atmel Corporation, ATtiny24A Datasheet - Page 51

• Manufacturer Part Number: ATtiny24A
• Manufacturer: Atmel Corporation

Specifications of ATtiny24A

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.3.3
9.3.4
8183D–AVR–04/11
GIFR – General Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
• Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
• Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[11:8] pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8
Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[11:8] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[11:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x3A (0x5A)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
INTF0
R
R/W
6
–
0
6
0
PCIF1
R
5
–
0
R/W
5
0
R
4
–
0
PCIF0
R/W
4
0
PCINT11
R/W
3
0
R
3
–
0
ATtiny24A/44A/84A
PCINT10
R/W
2
0
R
2
–
0
PCINT9
R/W
1
0
R
1
–
0
PCINT8
R/W
R
0
0
0
–
0
PCMSK1
GIFR
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