ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 15

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.9
4.9.1
4.9.2
8008H–AVR–04/11
Register Description
SPH and SPL — Stack Pointer Registers
SREG – Status Register
• Bits 9:0 – SP[10:0]: Stack Pointer
The Stack Pointer register points to the top of the stack, which is implemented growing from
higher memory locations to lower memory locations. Hence, a stack PUSH command decreases
the Stack Pointer.
The stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled.
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
Initial Value
Read/Write
Bit
0x3E (0x5E)
0x3D (0x5D)
Bit
Read/Write
Initial Value
Bit
0x3F (0x5F)
Read/Write
Initial Value
RAMEND
R/W
SP7
R/W
15
7
0
I
R
0
–
7
RAMEND
R/W
SP6
R/W
14
6
T
0
R
0
–
6
⊕
V
RAMEND
R/W
SP5
R/W
H
13
5
0
R
0
–
5
RAMEND
R/W
SP4
R/W
12
S
4
0
R
0
–
4
RAMEND
R/W
SP3
R/W
11
V
3
0
R
–
3
0
RAMEND
R/W
SP2
R/W
10
N
2
0
R
2
0
–
RAMEND
RAMEND
R/W
R/W
SP9
SP1
R/W
Z
1
0
9
1
ATtiny48/88
RAMEND
RAMEND
R/W
R/W
R/W
SP8
SP0
C
0
0
8
0
SREG
SPH
SPL
15