ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 160

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.11.6
15.11.7
160
ATtiny48/88
TWAMR – TWI (Slave) Address Mask Register
TWHSR – TWI High Speed Register
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
detail.
Figure 15-22. TWI Address Match Logic, Block Diagram
• Bit 0 – Res: Reserved Bit
This bit is reserved and will always read zero.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – TWHS: TWI High Speed Enable
TWI High Speed mode is enabled by writing this bit to one. In this mode the undivided system
clock is selected as TWI clock. See
The TWI High Speed mode requires that the high-speed clock, clk
higher than the I/O clock frequency, clk
frequency clk
been selected as source clock, the user must set the prescaler to scale the system clock (and,
hence, the I/O clock) down to 4 MHz. For more information about clock systems, see
System” on page
Bit
(0xBD)
Read/Write
Initial Value
Bit
(0xBE)
Read/Write
Initial Value
TWAMR0
Address
TWAR0
Bit 0
I/O
is scaled down by a factor of 2. For example, if the internal 8 MHz oscillator has
R/W
R
7
0
7
–
0
28.
R/W
R
6
0
6
–
0
Address Bit Comparator 6..1
R/W
R
5
0
Address Bit Comparator 0
5
–
0
Figure 6-1 on page
I/O
TWAM[6:0]
. This means the user must make sure the I/O clock
R/W
R
4
0
4
–
0
Figure 15-22
R/W
R
3
0
3
–
0
28.
R/W
shown the address match logic in
R
2
0
2
–
0
TWIHS
R/W
R
1
0
1
–
0
, is exactly two times
TWHS
R/W
Address
R
Match
0
–
0
0
0
8008H–AVR–04/11
TWAMR
TWHSR
“Clock