ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 202

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.3.1
21.3.2
202
ATtiny48/88
Pin Mapping
Programming Algorithm
The pin mapping is listed in
Table 21-7.
When writing serial data to the ATtiny48/88, data is clocked on the rising edge of SCK. When
reading data from the ATtiny48/88, data is clocked on the falling edge of SCK. See
on page 217
To program and verify the ATtiny48/88 in the serial programming mode, the following sequence
is recommended (See Serial Programming Instruction set in
1. Power-up sequence: apply power between V
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. The EEPROM can be programmed one byte or one page at a time.
set to “0”.
– In some systems, the programmer can not guarantee that SCK is held low during
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction.
– Whether the echo is correct or not, all four bytes of the instruction must be
– If the 0x53 did not echo back, give RESET a positive pulse and issue a new
a time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction.
– To ensure correct loading of the page, the data low byte must be loaded before data
– The Program Memory Page is stored by loading the Write Program Memory Page
– If polling (RDY/BSY) is not used, the user must wait at least t
– A: The EEPROM array is programmed one byte at a time by supplying the address
Symbol
power-up. In this case, RESET must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least t
See
t
transmitted.
Programming Enable command.
high byte is applied for a given address.
instruction with the 7 MSB of the address.
the next page (See
the Flash write operation completes can result in incorrect programming.
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling (RDY/BSY)
is not used, the user must wait at least t
MOSI
MISO
RST
SCK
Table 22-3 on page 209
and
Pin Mapping Serial Programming
Figure 22-10 on page 217
Table
Table
Pins
PB3
PB4
PB5
21-9). Accessing the serial programming interface before
21-7.
for definition of minimum pulse width on RESET pin,
for timing details.
WD_EEPROM
CC
I/O
O
I
I
and GND while RESET and SCK are
before issuing the next byte (See
RST
Table 21-8 on page
plus two CPU clock cycles.
WD_FLASH
Serial Data out
Serial Data in
Description
Serial Clock
before issuing
203):
8008H–AVR–04/11
Figure 22-9