ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 33

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8008H–AVR–04/11
and temperature dependent, as shown in
245
Table 6-5.
The main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V
The delay will not monitor the actual voltage and it will be required to select a delay longer than
the V
be used. A BOD circuit will ensure sufficient V
delay can be disabled. Disabling the time-out delay without utilizing a Brown-out Detection circuit
is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-down mode, V
at a sufficient level and only the start-up time is included.
CKSEL[1:0]
and
CC
rise time. If this is not possible, an internal or external Brown-out Detection circuit should
00
10
11
01
“Watchdog Oscillator Frequency vs. Temperature” on page
Length of Startup Sequence.
SUT[1:0]
XX
00
01
10
11
Number of WDT Cycles
“Watchdog Oscillator Frequency vs. VCC” on page
CC
4K (4,096)
8K (8,192)
Reserved
Reserved
before it releases the reset, and the time-out
0
246.
ATtiny48/88
Typical Time-out
CC
Reserved
Reserved
is assumed to be
64 ms
0 ms
4 ms
CC
33
.