ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 112

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.3.5.1
15.4
15.4.1
112
Accessing the NVM
ATtiny4/5/9/10
Addressing the Flash
Latching of Calibration Value
To ensure correct frequency of the calibrated internal oscillator the calibration value is automati-
cally written into the OSCCAL register during reset.
NVM lock bits, and all Flash memory sections are mapped to the data space as shown in
5-1 on page
in the data space.
The NVM Controller recognises a set of commands that can be used to instruct the controller
what type of programming task to perform on the NVM. Commands to the NVM Controller are
issued via the NVM Command Register. See
ister” on page
writing data to the NVM locations mapped to the data space.
When the NVM Controller is busy performing an operation it will signal this via the NVM Busy
Flag in the NVM Control and Status Register. See
Status Register” on page
as the busy flag is active. This is to ensure that the current command is fully executed before a
new command can start.
Programming any part of the NVM will automatically inhibit the following operations:
ATtiny4/5/9/10 support only external programming. Internal programming operations to NVM
have been disabled, which means any internal attempt to write or erase NVM locations will fail.
The data space uses byte accessing but since the Flash sections are accessed as words and
organized in pages, the byte-address of the data space must be converted to the word-address
of the Flash section. This is illustrated in
The most significant bits of the data space address select the NVM Lock bits or the Flash sec-
tion mapped to the data memory. The word address within a page (WADDR) is held by bits
[WADDRMSB:1], and the page address (PADDR) by bits [PADDRMSB:WADDRMSB+1].
Together, PADDR and WADDR form the absolute address of a word in the Flash section.
The least significant bit of the Flash section address is used to select the low or high byte of the
word.
• All programming to any other part of the NVM
• All reading from any NVM location
15. The NVM can be accessed for read and programming via the locations mapped
116. After the selected command has been loaded, the operation is started by
116. The NVM Command Register is blocked for write access as long
Figure
“NVMCMD - Non-Volatile Memory Command Reg-
15-1. Also, see
“NVMCSR - Non-Volatile Memory Control and
Table 15-3 on page
8127E–AVR–11/11
110.
Figure