ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 68

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.8.5
68
ATtiny4/5/9/10
Phase and Frequency Correct PWM Mode
Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR0x Registers are written. As the third period shown in
changing the TOP actively while the Timer/Counter is running in the phase correct mode can
result in an unsymmetrical output. The reason for this can be found in the time of update of the
OCR0x Register. Since the OCR0x update occurs at TOP, the PWM period starts and ends at
TOP. This implies that the length of the falling slope is determined by the previous TOP value,
while the length of the rising slope is determined by the new TOP value. When these two values
differ the two slopes of the period will differ in length. The difference in length gives the unsym-
metrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM0x1:0 to three (See
The actual OC0x value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x
Register at the compare match between OCR0x and TCNT0 when the counter increments, and
clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM03:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR0x Register is updated by the OCR0x Buffer Register, (see
10 on page 67
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and
and
Figure 11-11 on page
f
OCnxPCPWM
69).
=
---------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
Figure 11-10 on page 67
Table 11-4 on page
8127E–AVR–11/11
Figure 11-
illustrates,
75).