ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 66

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.8.4
66
ATtiny4/5/9/10
Phase Correct PWM Mode
The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP
value. The ICR0 Register is not double buffered. This means that if ICR0 is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICR0 value written is lower than the current value of TCNT0. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCR0A Register however, is double buffered. This feature allows the OCR0A I/O location
to be written anytime. When the OCR0A I/O location is written the value written will be put into
the OCR0A Buffer Register. The OCR0A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT0 matches TOP. The update is done
at the same timer clock cycle as the TCNT0 is cleared and the TOV0 flag is set.
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using
ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR0A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three (see
OC0x value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x Register at
the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR0x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM0x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform
generated will have a maximum frequency of f
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM03:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is
cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
f
OCnxPWM
=
0
A
---------------------------------- -
N
= f
⋅
(
clk_I/O
f
clk_I/O
1
+
TOP
/2 when OCR0A is set to zero (0x0000).
Table 11-3 on page
)
75). The actual
8127E–AVR–11/11