ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 77
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ATtiny88
Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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10.4
10.4.1
10.4.2
8008H–AVR–04/11
Register Description
MCUCR – MCU Control Register
PORTCR – Port Control Register
Table 10-13. Overriding Signals for Alternate Functions in PD[3:0]
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 61
• Bits 7:4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see
• Bits 3:0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn}
= 0b01). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD)
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x12 (0x32)
Read/Write
Initial Value
Signal
Name
PUOE
PUO
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD3/INT1/PCINT19
0
0
0
0
0
0
INT1 ENABLE +
PCINT19 • PCIE2
1
PCINT19 INPUT
INT1 INPUT
–
BBMD
R/W
R
7
–
0
7
0
“Break-Before-Make Switching” on page
BBMC
BPDS
R/W
R/W
6
0
6
0
for more details about this feature.
PD2/INT0/PCINT18
0
0
0
0
0
0
INT0 ENABLE +
PCINT18 • PCIE1
1
PCINT18 INPUT
INT0 INPUT
–
BPDSE
BBMB
R/W
R/W
5
0
5
0
BBMA
PUD
R/W
R/W
4
0
4
0
PUDD
R/W
PD1/PCINT17
0
0
0
0
0
0
PCINT17 • PCIE2
1
PCINT17 INPUT
–
R
3
–
0
3
0
62.
PUDC
R/W
R
2
–
0
2
0
PUDB
R/W
R
1
–
0
1
0
ATtiny48/88
PD0/PCINT16
0
0
0
0
0
0
PCINT16 • PCIE2
1
PCINT16 INPUT
–
PUDA
R/W
R
0
–
0
0
0
PORTCR
MCUCR
“Con-
77