ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 8
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ATtiny88
Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny88-12AU
Manufacturer:
ATMEL
Quantity:
2 165
Company:
Part Number:
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Manufacturer:
Atmel
Quantity:
7 370
Company:
Part Number:
ATtiny88-15MZ
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATtiny88-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL
Quantity:
5 000
Company:
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny88-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny88-MUR
Manufacturer:
AT
Quantity:
20 000
4. AVR CPU Core
4.1
4.2
8
Introduction
Architectural Overview
ATtiny48/88
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Control Lines
Instruction
Instruction
Program
Memory
Register
Decoder
Block Diagram of the AVR Architecture
Flash
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
Comparator
I/O Module1
I/O Module 2
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
Unit
SPI
8008H–AVR–04/11