ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 155
ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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13.14 Register Descriptions – Port Configuration
13.14.1
13.14.2
13.14.3
8331A–AVR–07/11
MPCMASK – Multi-pin Configuration Mask Register
VPCTRLA – Virtual Port-map Control Register A
VPCTRLB – Virtual Port-map Control Register B
• Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask
The MPCMASK register enables configuration of several pins of a port at the same time. Writing
a one to bit n makes pin n part of the multi-pin configuration. When one or more bits in the MPC-
MASK register is set, writing any of the PINnCTRL registers will update only the PINnCTRL
registers matching the mask in the MPCMASK register for that port. The MPCMASK register is
automatically cleared after any PINnCTRL register is written.
• Bit 7:4 – VP1MAP: Virtual Port 1 Mapping
These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN,
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 – VP0MAP: Virtual Port 0 Mapping
These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN,
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 7:4 – VP3MAP: Virtual Port 3 Mapping
These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN,
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
VP1MAP[3:0]
VP3MAP[3:0]
Table 13-6
Table 13-6
Table 13-6
R/W
R/W
R/W
5
0
5
0
5
0
for configuration.
for configuration.
for configuration.
R/W
R/W
R/W
4
0
4
0
4
0
MPCMASK[7:0]
R/W
R/W
R/W
Atmel AVR XMEGA AU
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
VP0MAP[3:0]
VP2MAP[3:0]
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
MPCMASK
VPCTRLA
VPCTRLB
155
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