ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 175

• Manufacturer Part Number: ATxmega128A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3U

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.8.4
8331A–AVR–07/11
Dual-slope PWM
to TOP and then restarts from BOTTOM. The waveform generator (WG) output is set on the
compare match between the CNT and CCx registers and cleared at TOP.
Figure 14-15. Single-slope pulse width modulation.
The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003),
and the maximum resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for single-slope PWM (R
The single-slope PWM frequency (f
eral clock frequency (fclk
where N represents the prescaler divider used. The waveform generated will have a maximum
frequency of half of the peripheral clock frequency (fclk
and no prescaling is used. This also applies when using the hi-res extension, since this
increases the resolution and not the frequency.
For dual-slope PWM generation, the period (T) is controlled by PER, while CCx registers control
the duty cycle of the WG output.
counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. The waveform gener-
ator output is set on BOTTOM, cleared on compare match when up-counting, and set on
compare match when down-counting.
R
f
PWM_SS
CNT
WG Output
PWM_SS
=
=
BOTTOM
log
---------------------------------- -
------------------------------ -
N PER
(
MAX
TOP
fclk
(
log
PER
PER
CCx
2 ( )
+
+
1
1
)
)
PER
Period (T)
), and can be calculated by the following equation:
Figure 14-16
PWM_SS
) depends on the period setting (PER) and the periph-
CCx=BOTTOM
shows how for dual-slope PWM the counter
Atmel AVR XMEGA AU
PER
) when CCA is set to zero (0x0000)
CCx=TOP
PWM_SS
"update"
"match"
):
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