SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 146
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SAM7XC512
Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Instruction Cycle Timings
6.2
6-4
Branch and branch with link
A branch instruction calculates the branch destination in the first cycle, while
performing a prefetch from the current PC. This prefetch is done in all cases because,
by the time the decision to take the branch has been reached, it is already too late to
prevent the prefetch.
During the second cycle a fetch is performed from the branch destination, and the return
address is stored in register 14 if the link bit is set.
The third cycle performs a fetch from the destination +L, refilling the instruction
pipeline. If the instruction is a branch with link (R14 is modified) four is subtracted from
R14 to simplify the return instruction from
subroutines to push R14 onto the stack and pop directly into PC upon completion.
The cycle timings are listed in Table 6-1 where:
•
•
•
Branch with link is not available in Thumb state.
pc is the address of the branch instruction
alu is the destination address calculated by the ARM7TDMI core
(alu) is the contents of that address.
Cycle
1
2
3
Note
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
alu
alu+L
alu+2L
MAS[1:0]
i
i
i
Table 6-1 Branch instruction cycle operations
0
0
0
nRW
Data
(pc+2L)
(alu)
(alu+L)
nMREQ
0
0
0
SEQ
0
1
1
ARM DDI 0029G
. This allows
nOPC
0
0
0
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