SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 278

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SAM7XC512

Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7XC512

Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Glossary
PSR
Reduced Instruction Set Computer
RISC
Saved Program Status Register
SBO
SBZ
Should Be One fields
Should Be Zero fields
Software Interrupt Instruction
SPSR
Stack pointer
Glossary-4
Also referred to as Current PSR (CPSR), to emphasize the distinction between it and
the Saved PSR (SPSR). The SPSR holds the value the PSR had when the current
function was called, and which will be restored when control is returned.
See Program Status Register.
A type of microprocessor that recognizes a lower number of instructions in comparison
with a Complex Instruction Set Computer. The advantages of RISC architectures are:
See also Complex Instruction Set Computer.
See Reduced Instruction Set Computer
The Saved Program Status Register which is associated with the current processor mode
and is undefined if there is no such Saved Program Status Register, as in User mode or
System mode.
See also Program Status Register.
See Should Be One fields.
See Should Be Zero fields.
Should be written as one (or all ones for bit fields) by software. Values other than one
produces unpredictable results.
See also Should Be Zero fields.
Should be written as zero (or all 0s for bit fields) by software. Values other than zero
produce unpredictable results.
See also Should Be One fields.
This instruction enters Supervisor mode to request a particular operating system
function.
See Saved Program Status Register.
A register or variable pointing to the top of a stack. If the stack is full stack the SP points
to the most recently pushed item, else if the stack is empty, the SP points to the first
empty location, where the next item will be pushed.
they can execute their instructions very fast because the instructions are so simple
they require fewer transistors, this makes them cheaper to produce and more
power efficient.
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G

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