SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 235
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SAM7XC512
Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
•
For input cells, the capture stage involves copying the value of the system input to the
core into the serial register. During shift, this value is output serially. The value applied
to the core from an input cell is either the system input or the contents of the serial
register and this is controlled by the multiplexor.
For output cells, capture involves placing the output value of a core into the serial
register. During shift, this value is serially output as before. The value applied to the
system from an output cell is either the core output, or the contents of the serial register.
All of the control signals for the scan cells are generated internally by the TAP
controller. The action of the TAP controller is determined by the current instruction and
the state of the TAP state machine.
There are three basic modes of operation of the scan chains, INTEST, EXTEST, and
SYSTEM that are selected by the various TAP controller instructions:
•
•
System data in
CAPTURE clock
SHIFT clock
SHIFT.
In INTEST mode, the core is internally tested. The data serially scanned in is
applied to the core and the resulting outputs are captured in the output cells and
scanned out.
In EXTEST mode, data is scanned onto the outputs of the core and applied to the
external system. System input data is captured in the input cells and then shifted
out.
Copyright © 1994-2001. All rights reserved.
Serial data out
Serial data in
register
latch
Shift
Figure B-4 Input scan cell
Data to core
Debug in Depth
B-17
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