SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 211
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SAM7XC512
Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
Name
CPB
Coprocessor busy
D[31:0]
Data bus
DBE
Data bus enable
DBGACK
Debug acknowledge
DBGEN
Debug enable
DBGRQ
Debug request
DBGRQI
Internal debug request
DIN[31:0]
Data input bus
Copyright © 1994-2001. All rights reserved.
Type
IC
IC
O8
IC
O4
IC
IC
O4
IC
Description
Placed LOW by the coprocessor when it is ready to start the operation
requested by the processor.
It is sampled by the processor when MCLK goes HIGH in each cycle in
which nCPI is LOW.
Used for data transfers between the processor and external memory.
During read cycles input data must be valid on the falling edge of
MCLK.
During write cycles output data remains valid until after the falling edge
of MCLK.
This bus is always driven except during read cycles, irrespective of the
value of BUSEN. Consequently it must be left unconnected if using the
unidirectional data buses.
See Chapter 3 Memory Interface.
Must be HIGH for data to appear on either the bidirectional or
unidirectional data output bus.
When LOW the bidirectional data bus is placed into a high impedance
state and data output is prevented on the unidirectional data output bus.
It can be used for test purposes or in shared bus systems.
When the processor is in a debug state this is HIGH.
A static configuration signal that disables the debug features of the
processor when held LOW.
This signal must be HIGH to allow the EmbeddedICE Logic to function.
This is a level-sensitive input, that when HIGH causes ARM7TDMI core
to enter debug state after executing the current instruction. This allows
external hardware to force the ARM7TDMI core into debug state, in
addition to the debugging features provided by the EmbeddedICE Logic.
See Appendix B Debug in Depth.
This is the logical OR of DBGRQ and bit 1 of the debug control register.
Unidirectional bus used to transfer instructions and data from the
memory to the processor.
This bus is only used when BUSEN is HIGH. If unused then it must be
tied LOW.
This bus is sampled during read cycles on the falling edge of MCLK.
Table A-3 Signal Descriptions (continued)
Signal Description
A-5
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