SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 54
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SAM7XC512
Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.6
2.6.1
2-8
Registers
The ARM-state register set
The ARM7TDMI processor has a total of 37 registers:
•
•
These registers are not all accessible at the same time. The processor state and operating
mode determine which registers are available to the programmer.
In ARM state, 16 general registers and one or two status registers are accessible at any
one time. In privileged modes, mode-specific banked registers become available. Figure
2-3 on page 2-10 shows which registers are available in each mode.
The ARM-state register set contains 16 directly-accessible registers, r0 to r15. A further
register, the CPSR, contains condition code flags and the current mode bits. Registers
r0 to r13 are general-purpose registers used to hold either data or address values.
Registers r14 and r15 have the following special functions:
Link register
Program counter
By convention, r13 is used as the Stack Pointer (SP).
In privileged modes, another register, the Saved Program Status Register (SPSR), is
accessible. This contains the condition code flags and the mode bits saved as a result of
the exception which caused entry to the current mode.
Banked registers are discrete physical registers in the core that are mapped to the
available registers depending on the current processor operating mode. Banked register
contents are preserved across operating mode changes.
31 general-purpose 32-bit registers
6 status registers.
Copyright © 1994-2001. All rights reserved.
Register 14 is used as the subroutine Link Register (LR).
Register r14 receives a copy of r15 when a Branch with Link (BL)
instruction is executed.
At all other times you can treat r14 as a general-purpose register.
The corresponding banked registers r14_svc, r14_irq, r14_fiq,
r14_abt and r14_und are similarly used to hold the return values
of r15 when interrupts and exceptions arise, or when BL
instructions are executed within interrupt or exception routines.
Register 15 holds the PC.
In ARM state, bits [1:0] of r15 are undefined and must be ignored.
Bits [31:2] contain the PC.
In Thumb state, bit [0] is undefined and must be ignored. Bits
[31:1] contain the PC.
ARM DDI 0029G
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