SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 181
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
8.12
8.12.1
ARM DDI 0165B
Load register
Interlocks
A load register operation typically occupies the Execute stage for one cycle. There
might be a number of cycles before the loaded value is available for later instructions.
A load to the PC occupies the Execute stage for five cycles.
Destination equals PC is not possible in Thumb state.
The result of an aligned word load instruction is not available until the end of the
Memory stage of the pipeline. If the following instruction requires the use of this result
then it must be interlocked so that the correct value is available. This interlock is
referred to as a single-cycle load-use interlock.
The following example incurs a single-cycle interlock:
LDR r0, [r1]
ADD r2, r0, r3
ORR r4, r4, r5
The following example does not incur an interlock:
LDR r0, [r1]
ORR r4, r4, r5
ADD r2, r0, r3
Unaligned word loads, load byte (
byte rotate unit in the Write stage of the pipeline. This introduces a two-cycle load-use
interlock, that can affect the two instructions immediately following the load
instruction.
The following example incurs a two-cycle interlock:
LDRB r0, [r1, #1]
ADD r2, r0, r3
ORR r4, r4, r5
The following example incurs a single-cycle interlock:
LDRB r0, [r1, #1]
ORR r4, r4, r5
ADD r2, r0, r3
Once an interlock has been incurred for one instruction it does not have to be incurred
for a later instruction.
Note
Copyright © 2000 ARM Limited. All rights reserved.
LDRB
), and load halfword (
LDRH
) instructions use the
Instruction Cycle Times
8-21
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