SAM9261 Atmel Corporation, SAM9261 Datasheet
SAM9261
Specifications of SAM9261
Related parts for SAM9261
SAM9261 Summary of contents
Page 1
... MHz On-chip Oscillator and two PLLs • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals ® ® Thumb Processor ® Acceleration ™ ® AT91SAM ARM-based Embedded MPU AT91SAM9261 6062N–ATARM–3-Oct-11 ...
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... Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA RoHS-compliant Package AT91SAM9261 2 Compliant ® Infrared Modulation/Demodulation 6062N–ATARM–3-Oct-11 ...
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... DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its inte- grated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance ...
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... Block Diagram Figure 2-1. AT91SAM9261 Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG XIN32 OSC RTT ...
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... Input Output Input Output Input Input Low Input ™ ETM Output Output Output Output AT91SAM9261 Comments 1. 1.95V and 3.0V to 3.6V 2.7V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Do not tie over VDDBU. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. No pull-up resistor. No pull-up resistor. ...
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... CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDCS NAND Flash Chip Select AT91SAM9261 6 Type Active Level Reset/Test I/O Low Input Input Debug Unit Input Output ...
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... Type Active Level SDRAM Controller Output Output High Output Low Output Output Low Output Low Output Multimedia Card Interface Output I/O I/O USART I/O Output Input Output Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O SPI I/O I/O I/O I/O Low Output Low AT91SAM9261 Comments 7 ...
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... USB Device Port Data - DDP USB Device Port Data + HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9261 8 Type Active Level Two-Wire Interface I/O I/O LCD Controller Output Output Output Output ...
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... Package and Pinout The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9261 Mechanical Character- istics” of the product datasheet. Figure 4-1. 6062N–ATARM–3-Oct-11 shows the orientation of the 217-ball LFBGA Package. ...
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... Pinout Table 4-1. AT91SAM9261 Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC D13 A10 XOUT32 D14 A11 XIN32 D15 A12 DDP D16 A13 HDPB D17 ...
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... GNDBU, GNDOSC and GNDPLL, respectively. 5.2 Power Consumption The AT91SAM9261 consumes about 550 µA of static current on VDDCORE at 25°C. This static current rises 5 the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise µA @85°C. ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU. AT91SAM9261 12 6062N–ATARM–3-Oct-11 ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6062N–ATARM–3-Oct-11 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9261 13 ...
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... Selection is made by BMS pin sampled at reset. • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors AT91SAM9261 14 ™ Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. ...
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... Next Pointer Support, forbids strong real-time constraints on buffer management. • Nineteen channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface 6062N–ATARM–3-Oct-11 AT91SAM9261 15 ...
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... Memories Figure 8-1. AT91SAM9261 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Supports ARM926EJ-S TCM interface at full processor speed 6062N–ATARM–3-Oct-11 ™ Instruction and Data), three different Slaves are Table 8-3 for details. List of Bus Matrix Masters List of Bus Matrix Slaves AT91SAM9261 ARM926 Instruction ARM926 Data PDC LCD Controller USB Host Internal SRAM Internal ROM ...
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... Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 8.1.1.1 Internal SRAM The AT91SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into three areas. Its Memory Mapping is detailed in • Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions ...
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... Note: 1. Configuration after reset. 8.1.1.2 Internal ROM The AT91SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000 also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset. 8.1.1.3 USB Host Port The AT91SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The reg- isters of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000 ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...
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... Fetch Internal Data Internal Fetch External Data External Fetch Internal Data Internal Data Figure 8-1 on page AT91SAM9261 Table 8-6. Start Address End Address 0x0000 0000 0x002F FFFF 0x0000 0000 0x002F FFFF 0x0040 0000 0x004F FFFF 0x0040 0000 0x004F FFFF 0x1000 0000 0x8FFF FFFF ...
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... EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 23 Figure 8-1 on page 16 peripherals. AT91SAM9261 22 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6062N–ATARM–3-Oct-11 ...
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... Power Management UHPCK PLLACK Controller LCDCK MCK PLLBCK pmc_irq int idle periph_irq{2..4] irq0-irq2 dbgu_rxd PIO fiq Controllers dbgu_txd AT91SAM9261 nirq nfiq ice_nreset ntrst ARM926EJ-S force_ntrst proc_nreset PCK debug jtag_nreset Boundary Scan TAP Controller MCK Bus Matrix periph_nreset UDPCK periph_clk[10] USB Device ...
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... Embeds Two PLLs – Outputs 80 to 240 MHz clocks – Integrates an input divider to increase output accuracy – 1 MHz minimum input frequency • Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. AT91SAM9261 24 Clock Generator Block Diagram Clock Generator XIN32 Slow Clock Oscillator ...
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... Divider Prescaler MAINCK /1,/2,/4 PLLACK /1,/2,/4,...,/64 PLLBCK Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK PLLBCK ® ® /WindowsCE compliant tick generator AT91SAM9261 Processor Clock PCK Controller int Idle Mode MCK APB Peripherals Clock Controller periph_clk[2..21] ON/OFF AHB Peripherals Clock Controller HCKx ON/OFF Prescaler pck[0 ...
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... Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support AT91SAM9261 26 interrupts processor Generator ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 6062N–ATARM–3-Oct-11 peripherals AT91SAM9261 27 ...
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... Note: AT91SAM9261 28 Figure 8-1 on page defines the Peripheral Identifiers of the AT91SAM9261. A peripheral identifier is Peripheral Identifiers Peripheral Mnemonic Peripheral Name AIC Advanced Interrupt Controller SYSIRQ System Interrupt PIOA Parallel I/O Controller A PIOB Parallel I/O Controller B PIOC Parallel I/O Controller C - Reserved ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions page 33 lers. The two columns “Function” and “Comments” have been inserted for the user’s own comments ...
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... Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.10 Interrupt Lines • Using FIQ prevents using the USART0 control signals. • Using IRQ0 prevents using the NWAIT EBI signal. • Using the IRQ1 and/or IRQ2 prevents using the SPI1. AT91SAM9261 30 6062N–ATARM–3-Oct-11 ...
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... Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP A23 VDDIOP A24 VDDIOP AT91SAM9261 Function Comments 31 ...
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... PB27 SPI1_NPCS1 LCDD22 PB28 SPI1_NPCS0 LCDD23 PB29 SPI1_SPCK IRQ2 PB30 SPI1_MISO IRQ1 PB31 SPI1_MOSI PCK2 Note: 1. PB3 is multiplexed with BMS signal. Care should be taken during reset time. AT91SAM9261 32 Application Usage Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP (1) See footnote I/O VDDIOP ...
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... Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP A25 VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM AT91SAM9261 Function Comments 33 ...
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... Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7 AT91SAM9261 34 IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. ...
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... Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used 6062N–ATARM–3-Oct-11 AT91SAM9261 35 ...
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... RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps AT91SAM9261 36 fifteen peripherals Sensors and data per chip select ...
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... Each MCI has two slots, each supporting – One slot for one MultiMedia Card bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 6062N–ATARM–3-Oct-11 AT91SAM9261 2 S, TDM Buses, Magnetic Card Reader and 37 ...
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... STN • bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048 x 2048 AT91SAM9261 38 Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode ...
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... ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA • separate instruction and data TCM interfaces 6062N–ATARM–3-Oct-11 ™ processor is a member of the ARM9 ™ integer core ® AHB bus interfaces AT91SAM9261 ™ family of general-purpose micropro- 39 ...
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... Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC AT91SAM9261 40 ARM926EJ-S Coprocessor Interface Droute ...
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... User mode is the usual ARM program execution state used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 6062N–ATARM–3-Oct-11 AT91SAM9261 41 ...
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... Table 11-1 Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR AT91SAM9261 42 shows all the registers in all modes. ™ ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode ...
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... The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 6062N–ATARM–3-Oct-11 AT91SAM9261 43 ...
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... Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) AT91SAM9261 Reserved Jazelle state bit ...
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... ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 6062N–ATARM–3-Oct-11 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. AT91SAM9261 45 ...
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... MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP AT91SAM9261 46 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR AT91SAM9261 Mnemonic Operation MRRC Move double from coprocessor Alternative move of ARM reg to MCR2 coprocessor MCRR Move double to coprocessor Alternative Coprocessor Data ...
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... ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Register AT91SAM9261 48 Thumb Instruction Mnemonic List (Continued) Operation Logical Shift Left Arithmetic Shift Right Multiply Branch ...
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... Register locations 0, 5 and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. AT91SAM9261 Read/Write Read/write Read/write ...
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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. AT91SAM9261 50 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91SAM9261 ® , Windows CE, and Subpage Size - 16K bytes 1K byte - 51 ...
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... The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. AT91SAM9261 52 6062N–ATARM–3-Oct-11 ...
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... DCache can be enabled or disabled by writing either bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 6062N–ATARM–3-Oct-11 AT91SAM9261 53 ...
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... TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools. AT91SAM9261 54 6062N–ATARM–3-Oct-11 ...
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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 6062N–ATARM–3-Oct-11 AT91SAM9261 55 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9261 56 gives an overview of the supported transfers and different kinds of transactions they Single transfer of word, half word, or byte: • ...
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... AT91SAM9261 Debug and Test 12.1 Overview The AT91SAM9261 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO ...
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... ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example AT91SAM9261 58 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Trace Port Interface Interface ICE/JTAG Trace Connector Connector RS232 AT91SAM9261 Connector AT91SAM9261-based Application Board Host Debugger Terminal 6062N–ATARM–3-Oct-11 ...
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... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM9261 AT91SAM9261-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Clock Test Data In ...
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... It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. AT91SAM9261 60 Debug and Test Pin List ...
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... Thus the maximum frequency of all the trace port signals does not exceed one half of the ARM926EJ-S clock speed. The Embedded Trace Macrocell input and output resources are not used in the AT91SAM9261. The Embedded Trace is a real-time trace module with the capability of tracing the ARM9EJ-S instructions and data ...
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... In range mode, the address comparators are arranged in pairs to form a virtual address range resource. Details of the address comparator programming are: • The first comparator is programmed with the range start address. • The second comparator is programmed with the range end address. AT91SAM9261 62 Trace ARM926EJ-S Control ...
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... Internal Fetch Internal Data Internal Fetch External Data External Fetch Internal Data Internal Data AT91SAM9261 Start Address End Address 0x0000 0000 0x002F FFFF 0x0000 0000 0x002F FFFF 0x0040 0000 0x004F FFFF 0x0040 0000 0x004F FFFF 0x1000 0000 0x8FFF FFFF 0x1000 0000 ...
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... It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. AT91SAM9261 64 ARM926EJ-S Clock Trace Clock TraceData Half-rate Clocking Mode AT91SAM9261-based Application Board Pin 1Chamfer Figure 12-6. The view of 6062N–ATARM–3-Oct-11 ...
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... The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associ- ated control signals. Each AT91SAM9261 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad ...
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... AT91SAM9261 66 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name D10 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 420 419 D11 418 417 416 D12 415 414 413 412 D13 411 410 409 D14 408 407 406 D15 405 404 403 PC16 402 401 ...
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... AT91SAM9261 68 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name PC31 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 348 347 PC28 346 345 344 343 PC29 342 341 340 339 PC0 338 337 336 335 PC1 334 333 332 331 PC2 330 329 328 ...
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... AT91SAM9261 70 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 276 275 PA0 274 273 272 271 PA1 270 269 268 267 PA2 266 265 264 263 PA3 262 261 260 259 PA4 258 257 256 ...
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... AT91SAM9261 72 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 204 203 PA18 202 201 200 199 PA19 198 197 196 195 PA20 194 193 192 191 PA21 190 189 188 187 PA22 186 185 184 ...
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... AT91SAM9261 74 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name PA27 PA28 PA29 PA30 PA31 PB0 PB1 PB2 PB3 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 132 131 PB4 130 129 128 127 PB5 126 125 124 123 PB6 122 121 120 119 PB7 118 117 116 115 PB8 114 113 112 ...
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... Table 12-3. Bit Number AT91SAM9261 76 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 96 95 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 62 61 Pin Type ...
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... Table 12-3. Bit Number 6062N–ATARM–3-Oct-11 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 60 59 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 ...
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... Table 12-3. Bit Number AT91SAM9261 78 AT91SAM9261 JTAG Boundary Scan Register (Continued) Pin Name 24 23 PB31 A[15: A10 07 SDA10 06 A11 05 A12 04 A13 03 A14 02 A15 01 A16 00 A17 Pin Type Associated BSR Cells INPUT ...
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... MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_803F. 6062N–ATARM–3-Oct- PART NUMBER MANUFACTURER IDENTITY AT91SAM9261 26 25 PART NUMBER MANUFACTURER IDENTITY ...
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... AT91SAM9261 80 6062N–ATARM–3-Oct-11 ...
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... AT91SAM9261 Boot Program 13.1 Description The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial flash Boot program and Data- ® ...
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... Figure 13-1. Boot Program Algorithm Flow Diagram SPI Serialflash Boot No SPI Dataflash Boot No NandFlash Boot No SD Card Boot No EEPROMBoot No AT91SAM9261 82 Device Setup Yes Download from Serial flash NPCS0 Timeout < Yes Download from Dataflash NPCS0 Timeout < Yes Download from NandFlash Timeout < 50ms ...
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... Jump to SAM-BA Boot sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port 6062N–ATARM–3-Oct-11 defines the crystals supported by the Boot Program. Crystals Supported by Software Auto-Detection (MHz) 3.2768 3.6864 4.608 4.9152 6.144 6.4 7.864320 8.0 12.0 12.288 16.0 17.734470 AT91SAM9261 3.84 4.0 5.0 5.24288 6.5536 7.159090 9.8304 10.0 13.56 14.31818 18.432 20.0 83 ...
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... This information is described below. 6062N–ATARM–3-Oct-11 0x0000_0000 Internal ROM 0x0030_0000 Internal SRAM Offset (24 bits) AT91SAM9261 0x0000_0000 Internal SRAM REMAP 0x0010_0000 Internal ROM “Structure of ARM Vector 6” on page 84 ...
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... This application may be the application code or a second-level bootloader. 6062N–ATARM–3-Oct-11 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 AT91SAM9261 0 85 ...
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... LDR or Branch instruction Yes Read the SerialFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9261 No Jump to next boot solution No 86 ...
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... LDR or Branch instruction Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9261 No Jump to next boot solution No 87 ...
Page 88
... Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument AT91SAM9261 “Valid Image Detection” on page 84 “Valid Image Detection” on page 84 Table 13-2. Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# ...
Page 89
... CRC16 Figure 13-8 6062N–ATARM–3-Oct-11 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. : Number of bytes in hexadecimal to receive NbOfBytes to 01) shows a transmission using this protocol. AT91SAM9261 89 ...
Page 90
... The device handles standard requests as defined in the USB Specification. Table 13-3. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION AT91SAM9261 90 Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ...
Page 91
... Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. contains a list of pins that are driven during the boot program execution. These pins AT91SAM9261 91 ...
Page 92
... SPI0 PIOC PIOC PIOC Address Bus Address Bus MCI0 MCI0 MCI0 MCI0 MCI0 MCI0 TWI TWI DBGU DBGU AT91SAM9261 92 Pins Driven during Boot Program Execution Pin MOSI MISO SPCK NPCS0 NANDCS NAND OE NAND WE NAND CLE NAND ALE MCDA0 MCCDA MCCK MCDA1 ...
Page 93
... Block Diagram Figure 14-1. Reset Controller Block Diagram Backup Supply 6062N–ATARM–3-Oct-11 Reset Controller Main Supply POR Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault AT91SAM9261 rstc_irq Reset State Manager proc_nreset user_reset periph_nreset exter_nreset backup_neset SLCK 93 ...
Page 94
... The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. AT91SAM9261 94 Figure 14-2 shows the block diagram of the NRST Manager. ...
Page 95
... The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling SLCK Core Supply POR output BMS Signal proc_nreset 6062N–ATARM–3-Oct-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs XXX BMS sampling delay = 3 cycles AT91SAM9261 ...
Page 96
... SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9261 96 shows how he General Reset affects the reset signals. Startup Time Processor Startup = 2 cycles XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles Any Freq. 0x0 = General Reset XXX 6062N– ...
Page 97
... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6062N–ATARM–3-Oct-11 Resynch. Processor Startup 2 cycles = 2 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9261 Any Freq. 0x1 = WakeUp Reset XXX 97 ...
Page 98
... ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. AT91SAM9261 Resynch ...
Page 99
... ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 6062N–ATARM–3-Oct-11 Any Freq. Resynch. Processor Startup 1 cycle = 2 cycles XXX Any EXTERNAL RESET LENGTH AT91SAM9261 0x3 = Software Reset 8 cycles (ERSTL=2) 99 ...
Page 100
... When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) AT91SAM9261 100 Any Freq. Processor Startup = 2 cycles Any XXX EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 0x2 = Watchdog Reset 6062N–ATARM–3-Oct-11 ...
Page 101
... If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. 6062N–ATARM–3-Oct-11 proc_nreset signal. AT91SAM9261 Figure 101 ...
Page 102
... Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9261 102 read RSTC_SR 2 cycle resynchronization 6062N–ATARM–3-Oct-11 ...
Page 103
... Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6062N–ATARM–3-Oct-11 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write AT91SAM9261 Reset Back-up Reset - 0x0000_0001 0x0000_0000 - 0x0000_0000 103 ...
Page 104
... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9261 104 KEY 21 ...
Page 105
... Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low AT91SAM9261 – – – – SRCMP NRSTL RSTTYP – ...
Page 106
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9261 106 29 28 ...
Page 107
... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9261 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 107 ...
Page 108
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9261 108 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 109
... Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6062N–ATARM–3-Oct-11 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only AT91SAM9261 Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 109 ...
Page 110
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9261 110 – ...
Page 111
... Returns the current value of the Real-time Timer. 6062N–ATARM–3-Oct- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9261 111 ...
Page 112
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9261 112 – ...
Page 113
... Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 6062N–ATARM–3-Oct-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9261 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 114
... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91SAM9261 114 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 16-2 APB cycle ...
Page 115
... Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 6062N–ATARM–3-Oct-11 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only AT91SAM9261 Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 115 ...
Page 116
... PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. AT91SAM9261 116 – ...
Page 117
... The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6062N–ATARM–3-Oct- – – – – – – – – – – – – AT91SAM9261 – – – – – – – – – – – PITS 117 ...
Page 118
... Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6062N–ATARM–3-Oct- PICNT CPIV CPIV PICNT CPIV CPIV AT91SAM9261 CPIV CPIV 118 ...
Page 119
... SHDN. 6062N–ATARM–3-Oct-11 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_SHMR RTTWK SHDW_SR set AT91SAM9261 SLCK Wake-up SHDN Shutdown Output Controller SHDW_SR Shutdown SHDW Type Input Output 119 ...
Page 120
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9261 120 SHDN ...
Page 121
... Name SHDW_CR SHDW_MR SHDW_SR KEY – – – – – – – – – pin. AT91SAM9261 Access Reset Write-only - Read-write 0x0000_0303 Read-only 0x0000_0000 – – – – – – – ...
Page 122
... Because of the internal synchronization of WKUP0, the (CPTWK Slow Clock cycles after the event on WKUP. • RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller The RTT Alarm signal forces the de-assertion of the AT91SAM9261 122 – ...
Page 123
... At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. 6062N–ATARM–3-Oct- – – – – – – – – – – – – AT91SAM9261 – – – – – RTTWK – – – – – WAKEUP0 123 ...
Page 124
... AT91SAM9261 124 6062N–ATARM–3-Oct-11 ...
Page 125
... The System Controller embeds 4 general-purpose backup registers. 18.2 General Purpose Backup Registers (GPBR) User Interface Table 18-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xC General Purpose Backup Register 3 6062N–ATARM–3-Oct-11 AT91SAM9261 Name SYS_GPBR0 ... SYS_GPBR 3 Access Reset Read-write – ... ... Read-write – 125 ...
Page 126
... General Purpose Backup Register x Register Name:SYS_GPBRx Addresses: 0xFFFFFD50 [0], 0xFFFFFD54 [1], 0xFFFFFD58 [2], 0xFFFFFD5C [3] Access Type: Read-write • GPBR_VALUEx: Value of GPBR x AT91SAM9261 126 GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx 6062N–ATARM–3-Oct-11 ...
Page 127
... AT91SAM9261 Bus Matrix 19.1 Overview The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 5 AHB Masters to 5 AHB Slaves. The Bus Matrix user interface is compliant with the ARM Advanced Peripheral Bus and provides 5 Special Function Registers (MATRIX_SFR) that allow the Bus Matrix to support application-specific features ...
Page 128
... Any request attempted by this fixed default master does not cause any latency, whereas other non-privileged masters still obtain one latency cycle. This technique can be used for masters that perform mainly single accesses. AT91SAM9261 128 6062N–ATARM–3-Oct-11 ...
Page 129
... Slave Configuration Register 4 0x0018 - 0x0020 Reserved 0x0024 MATRIX TCM Configuration Register 0x028 - 0x002C Reserved 0x0030 EBI Chip Select Assignment Register 0x0034 USB Pad Pull-up Control Register 6062N–ATARM–3-Oct-11 AT91SAM9261 Name Access MATRIX_MCFG Write only MATRIX_SCFG0 Read-write MATRIX_SCFG1 Read-write MATRIX_SCFG2 Read-write MATRIX_SCFG3 ...
Page 130
... RCBx: Remap Command Bit for AHB Master effect 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x. AT91SAM9261 130 – – – – ...
Page 131
... FIXED_DEFMSTR: Fixed Index of Default Master This is the index of the Fixed Default Master for this slave. 6062N–ATARM–3-Oct- – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT91SAM9261 – – – DEFMSTR_TYPE – – – 131 ...
Page 132
... ITCM_SIZE: Size of ITCM enabled memory block 0000 0KB (No ITCM Memory) 0101 0110 0111 Others: Reserved • DTCM_SIZE: Size of DTCM enabled memory block 0000 0 KB (No DTCM Memory) 0101 0110 0111 Others: Reserved AT91SAM9261 132 – – – – ...
Page 133
... EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply EBI D0 - D15 Data Bus bits are not internally pulled-up. 6062N–ATARM–3-Oct- – – – – – – EBI_CS5A EBI_CS4A EBI_CS3A AT91SAM9261 – – – – – – – – – 3 ...
Page 134
... Access Type:Read-write Reset: 0x0000_0000 31 30 Reserved UDP_PUP_ON 23 22 – – – – – – • UDP_PUP_ON: UDP Pad Pull-up Enable 0: Pad pull-up disabled 1: Pad pull-up enabled AT91SAM9261 134 – – – – – – – – – – ...
Page 135
... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 6062N–ATARM–3-Oct-11 AT91SAM9261 135 ...
Page 136
... Block Diagram Figure 20-1 Figure 20-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9261 136 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Logic Static Memory Controller NAND Flash Logic CompactFlash Logic Chip Select Assignor ...
Page 137
... NWR0 - NWR3 Write Signals NBS0 - NBS3 Byte Mask Signals SDA10 SDRAM Address 10 Line 6062N–ATARM–3-Oct-11 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91SAM9261 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 138
... A25 A[2:25] NCS0 CS NCS1/SDCS CS NCS2 CS NCS3/NANDCS CS NCS4/CFCS0 CS AT91SAM9261 138 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported ...
Page 139
... DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – A10 – – – A[11:12] – – – BA0 – BA1 – – – – – – REG AT91SAM9261 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices ( (2) (3) WE NUB (2) (4) WE ...
Page 140
... CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For “CE don’t care” NAND Flash devices, it can be connected to either NCS3/NANDCS or to any free PIO line. AT91SAM9261 140 Pins of the Interfaced Device ...
Page 141
... A10 A16/BA0 RAS BA0 A17/BA1 CAS BA1 DQM NBS2 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0-D7 D8-D15 CS OE NRD/NOE NRD/NOE WE A0/NWR0/NBS0 NWR1/NBS1 AT91SAM9261 SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 ...
Page 142
... NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. AT91SAM9261 142 6062N–ATARM–3-Oct-11 ...
Page 143
... Offset 0x0040 0000 Offset 0x0000 0000 The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). CompactFlash Mode Selection AT91SAM9261 True IDE Alternate Mode Space True IDE Mode Space I/O Mode Space Common Memory Mode Space ...
Page 144
... CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. 20-4 on page 145 Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. AT91SAM9261 144 CFCE1 DBW ...
Page 145
... A20 NRD NWR0_NWE CFOE CFWE NRD NWR0_NWE and Table 20-9 on page 146 Table 20-9 on page 146 remain shared between all memory areas when the cor- CompactFlash Signals CS5A = 1 CFCS1 AT91SAM9261 CompactFlash Logic CFOE 1 1 CFWE 1 0 CFIOR 1 CFIOW 1 1 CFIOR ...
Page 146
... The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller section. AT91SAM9261 146 Access to CompactFlash Device CompactFlash Signals ...
Page 147
... NCS6 and NCS7 (i.e., between 0x70000000 and 0x8FFF FFFF) may lead to an unpredictable outcome. 6062N–ATARM–3-Oct-11 EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NRD/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT AT91SAM9261 CompactFlash Connector D[15:0] DIR /OE _CD1 _CD2 /OE A[10:0] _REG _OE _WE _IORD _IOWR _CE1 _CE2 _WAIT ...
Page 148
... NAND Flash device are distinguished by using their address within the NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) sig- nals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. AT91SAM9261 148 MUX Logic CS3A ...
Page 149
... Figure 20-7. NAND Flash Application Example Note: 6062N–ATARM–3-Oct-11 D[7:0] A[22:21] NCS3/NANDCS EBI NCS6/NANDOE NCS7/NANDWE PIO PIO The External Bus Interface is also able to support 16-bits devices. AT91SAM9261 AD[7:0] ALE CLE Not Connected NAND Flash NOE NWE CE R/B 149 ...
Page 150
... Select Assignment Register located in the bus matrix memory space. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. AT91SAM9261 150 ...
Page 151
... C7 100NF C7 100NF DQML VDDQ 39 DQMH 28 VSS 17 41 CAS VSS 18 54 RAS VSS 6 VSSQ 12 VSSQ VSSQ VSSQ 256 Mbits TSOP54 PACKAGE AT91SAM9261 DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 DQ4 ...
Page 152
... PIO controller. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. AT91SAM9261 152 U1 U1 ...
Page 153
... R/B 10K 10K 3V3 10K 10K 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 N.C 10 N.C 11 N.C 14 N.C 15 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 N.C 34 N TSOP48 PACKAGE AT91SAM9261 I/O9 D10 31 I/O10 D11 33 I/O11 D12 41 I/O12 D13 43 I/O13 D14 45 I/O14 D15 47 I/O15 39 N ...
Page 154
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. AT91SAM9261 154 D[0..15] A[1..22] ...
Page 155
... SN74ALVC125 10K 10K RDY/BSY 11 12 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K WAIT GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9261 MEMORY & I/O MODE 3V3 J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 ...
Page 156
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9261 156 6062N–ATARM–3-Oct-11 ...
Page 157
... INTRQ 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K IORDY 4 2 3V3 3 GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9261 TRUE IDE MODE 3V3 J1 J1 CF_D15 D15 VCC CF_D14 100NF 100NF 30 D14 CF_D13 D13 VCC CF_D12 ...
Page 158
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9261 158 6062N–ATARM–3-Oct-11 ...
Page 159
... Write or Byte Select Access” on page 161 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 161 AT91SAM9261 Type Output Output Output Output Output ...
Page 160
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9261 160 128K x 8 SRAM ...
Page 161
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6062N–ATARM–3-Oct-11 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-5 AT91SAM9261 Figure 21-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 162
... Figure 21-3. Figure 21-4. Figure 21-5. Memory Connection for a 32-bit Data Bus AT91SAM9261 162 Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] D[31:16] D[15:0] A[20:2] NBS0 SMC NBS1 NBS2 NBS3 NWE NRD NCS[2] ...
Page 163
... Byte Select Access is used to connect two 16-bit devices. Figure 21-7 mode, on NCS3 (BAT = Byte Select Access). 6062N–ATARM–3-Oct-11 Figure 21-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91SAM9261 163 ...
Page 164
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9261 164 Connection 8-bit Devices on a 16-bit Bus: Byte Write Option ...
Page 165
... Byte Select Byte Write Byte Select NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91SAM9261 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable ...
Page 166
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9261 166 Figure 21-8. MCK A[25:2] ...
Page 167
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6062N–ATARM–3-Oct-11 AT91SAM9261 Figure 21-9). 167 ...
Page 168
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9261 168 MCK A[25:2] ...
Page 169
... Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS NBS0,NBS1, NBS2,NBS3, A0, A1 6062N–ATARM–3-Oct-11 MCK A[25:2] NRD NCS D[31:0] shows the typical read cycle of an LCD module. The read data is valid t MCK A[25:2] NRD NCS D[31:0] AT91SAM9261 t PACC Data Sampling t PACC Data Sampling after PACC 169 ...
Page 170
... NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle NBS0, NBS1, NBS2, NBS3, A0, A1 AT91SAM9261 170 MCK [25:2] A NWE NCS NWE_SETUP ...
Page 171
... Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6062N–ATARM–3-Oct-11 MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NCS D[31:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE AT91SAM9261 Figure NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE 21-13). How- 171 ...
Page 172
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9261 172 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is ...
Page 173
... NCS D[31:0] shows how the timing parameters are coded and their permitted range. Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91SAM9261 Permitted Range Coded Value Effective Value 0 ≤ ≤ ≤ ≤ 128+31 0 ≤ ≤ ≤ ≤ 256+63 0 ≤ ...
Page 174
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 Select 2. AT91SAM9261 174 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...
Page 175
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6062N–ATARM–3-Oct-11 NRD_CYCLE Read to Write Wait State (Figure 21-17). Figure AT91SAM9261 NWE_CYCLE Chip Select Wait State 21-19. (Figure 175 ...
Page 176
... D[31:0] Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9261 176 no hold write cycle Early Read wait state no hold write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 0) ...
Page 177
... Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code from a memory connected on this CS, may lead 6062N–ATARM–3-Oct-11 MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) wait state AT91SAM9261 read setup = 1 read cycle (READ_MODE = 0 or READ_MODE = 1) 177 ...
Page 178
... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9261 178 “Slow Clock Mode” on page Figure 21-16 on page 175 ...
Page 179
... NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6062N–ATARM–3-Oct-11 ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal DF illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), AT91SAM9261 Figure 21-21 shows the read oper- 179 ...
Page 180
... Figure 21-20. TDF Period in NRD Controlled Read Access (TDF = 2) Figure 21-21. TDF Period in NCS Controlled Read Operation (TDF = 3) AT91SAM9261 180 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] NRD controlled read operation MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] NCS controlled read operation ...
Page 181
... TDF optimization. 6062N–ATARM–3-Oct-11 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 Read to Write Wait State 21-23, Figure 21-24 and Figure 21-25 AT91SAM9261 NWE_SETUP= 3 write access on NCS0 (NWE controlled) illustrate the cases: 181 ...
Page 182
... A NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9261 182 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State ...
Page 183
... The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6062N–ATARM–3-Oct-11 read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State AT91SAM9261 write2 setup = 1 4 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 192 Slow Clock Mode (“Slow Clock Mode” on ...
Page 184
... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 21-27. Figure 21-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9261 184 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...
Page 185
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6062N–ATARM–3-Oct-11 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 AT91SAM9261 Assertion is ignored 0 0 185 ...
Page 186
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 6062N–ATARM–3-Oct- Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91SAM9261 Figure 21-28 and Figure 21-29. After Wait STATE Fig- 186 ...
Page 187
... Figure 21-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6062N–ATARM–3-Oct- Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 AT91SAM9261 Wait STATE Assertion is ignored 187 ...
Page 188
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-30. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 6062N–ATARM–3-Oct- minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 AT91SAM9261 WAIT STATE Fig- 188 ...
Page 189
... They are valid on all Table 21-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode Duration (cycles AT91SAM9261 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ ...
Page 190
... NWE_CYCLE = 3 SLOW CLOCK MODE WRITE AT91SAM9261 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State ...
Page 191
... Figure 21-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6062N–ATARM–3-Oct- IDLE STATE AT91SAM9261 NORMAL MODE WRITE Reload Configuration Wait State 191 ...
Page 192
... A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. shows the NRD and NCS timings in page mode access. tpa NRD_PULSE NCS_RD_PULSE AT91SAM9261 Table 21-7. ) takes longer than the subse- pa Figure 21-34 ...
Page 193
... Access time of subsequent accesses in the page sa ‘x’ No impact ) and the NRD_PULSE for accesses to the page ( shorter than the programmed value for Figure 21- AT91SAM9261 Table 21- Table 21-7 are identical, then the cur- illustrates access to an 8-bit memory device in ), even if sa 193 ...
Page 194
... Figure 21-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6062N–ATARM–3-Oct-11 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9261 NRD_PULSE 194 ...
Page 195
... SMC Mode Register 0xEC-0xFC Reserved 6062N–ATARM–3-Oct-11 Table 21-9. For each chip select, a set of 4 registers is used to pro- Table 21-9, “CS_number” denotes the chip select number. Name Access SMC_SETUP Read-write SMC_PULSE Read-write SMC_CYCLE Read-write SMC_MODE Read-write - AT91SAM9261 Reset 0 0x01010101 0x00010001 0x10001000 - - 195 ...
Page 196
... NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 6062N–ATARM–3-Oct- NCS_RD_SETUP NCS_WR_SETUP AT91SAM9261 NRD_SETUP NWE_SETUP 196 ...
Page 197
... The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 6062N–ATARM–3-Oct- NCS_RD_PULSE NRD_PULSE NCS_WR_PULSE NWE_PULSE AT91SAM9261 197 ...
Page 198
... NRD and NCS signals defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 6062N–ATARM–3-Oct- – – – NRD_CYCLE – – – NWE_CYCLE AT91SAM9261 – – NRD_CYCLE – – NWE_CYCLE 198 ...
Page 199
... PS – – TDF_MODE DBW – EXNW_MODE – NWAIT Mode 0 Disabled 1 Reserved 0 Frozen Mode 1 Ready Mode AT91SAM9261 – – PMEN TDF_CYCLES – – BAT – WRITE_MODE READ_MODE 199 ...
Page 200
... PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes 6062N–ATARM–3-Oct-11 Data Bus Width 0 8-bit bus 1 16-bit bus 0 32-bit bus 1 Reserved Page Size 0 4-byte page 1 8-byte page 0 16-byte page 1 32-byte page AT91SAM9261 200 ...