SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 193
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
8.18
8.18.1
ARM DDI 0165B
Cycle
Normal
1 cycle interlock
Data swap
Interlocks
1
2
1
2
3
A data swap is similar to a back-to-back load and store instruction. The data is read from
external memory in the second cycle and the contents of the register are written to the
external memory in the third cycle (which is merged with the first Execute cycle of the
next instruction).
The data swapped can be a byte or word quantity.
The swap operation might be aborted in either the read or the write cycle. An aborted
swap operation does not affect the destination register.
Data swap instructions are not available in Thumb state.
The DLOCK output of ARM9E-S is driven HIGH for both read and write cycles to
indicate to the memory system that it is an atomic operation.
A swap operation can cause one and two-cycle interlocks in a similar fashion to a load
register instruction.
Table 8-25 shows the cycle timing for the basic data swap operation.
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
Note
Copyright © 2000 ARM Limited. All rights reserved.
I cycle
InMREQ,
ISEQ
S cycle
I cycle
I cycle
S cycle
INSTR
(pc+2i)
-
(pc+3i)
(pc+2i)
-
-
(pc+3i)
DA
da
da
da
da
-
DnMREQ,
DSEQ
N cycle
N cycle
N cycle
N cycle
I cycle
Table 8-25 Data swap cycle timing
RDATA
(da)
-
(da)
-
-
Instruction Cycle Times
WDATA
-
Rd
-
Rd
-
8-33
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