SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 182

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8-22
instruction, but the second
For example, the following sequence incurs a two-cycle interlock on the first
LDRB
ADD
ADD
A two-cycle interlock refers to the number of unwaited ARM9E-S clock cycles to
which the interlock applies. If a multi-cycle instruction separates a load instruction and
the instruction using the result of the load, then no interlock can apply. The following
example does not incur an interlock:
LDRB
MUL
ADD
There is no forwarding path from loaded data to the C read port of the register bank,
which is used for the store data of
operand of multiply accumulate instructions. The result of a load must reach the Write
stage of the pipeline before it can be made available at the C read port, resulting in a
single-cycle load-use interlock from loaded data to the C read port.
The following example incurs a single-cycle interlock:
LDR
STR
The following example also incurs a single-cycle interlock:
LDR
MLA
The following example does not incur an interlock:
LDR
NOP ** Code to be changed to remove NOP **
STR
Most interlock conditions are determined when the instruction being interlocked is still
in the Decode stage of the pipeline. Load multiple and Store multiple instructions can
incur a Decode stage interlock when the base register is not available due to a previous
instruction. Store multiple instructions can also incur an Execute stage interlock when
the first register to be stored is not available due to a previous instruction. This is
referred to as a second-cycle interlock.
The following example incurs a single-cycle interlock:
LDR
STMIA
Copyright © 2000 ARM Limited. All rights reserved.
r0, [r1, #1]
r2, r0, r3
r4, r0, r5
r0, [r1]
r6, r7, r8
r4, r0, r5
r0, [r1]
r0, [r2]
r0, [r1]
r2, r3, r4, r0
r0, [r1]
r0, [r2]
r0, [r1]
r0, {r1-r2}
ADD
does not incur any interlocks:
STR
and
STM
instructions and for the accumulate
ARM DDI 0165B
ADD