SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 19

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.7
6249HS–ATARM–27-Jul-09
DMA Controller
• Acts as one Matrix Master
• Embeds 2 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
• Channel Control
– USART1 Transmit Channel
– USART0 Transmit Channel
– AC97 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC1 Transmit Channel
– SSC0 Transmit Channel
– DBGU Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– AC97 Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC1 Receive Channel
– SSC0 Receive Channel
– MCI1 Transmit/Receive Channel
– MCI0 Transmit/Receive Channel
– Source/destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
– Two 8-word FIFOs
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
lists
transfer. Writing a stream of data into non-contiguous fields in system memory.
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
AT91SAM9263
19