SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 101
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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4.3
ARM DDI0198D
Enabling the caches
On reset, the ICache and DCache entries are all invalidated and the caches are disabled.
The caches are not accessed for reads or writes. The caches are enabled using the I, C,
and M bits from CP15 c1, and can be enabled independently of one another. Table 4-1
gives the I and M bit settings for the ICache, and the associated behavior. The priority
of the TCM and cache behavior is described in TCM and cache access priorities on
page 4-8.
Table 4-2 gives the page table C bit settings for the ICache (CP15 c1 I bit = M bit = 1).
CP15
c1 I bit
0
1
1
Page
table
C bit
0
1
Copyright © 2001-2003 ARM Limited. All rights reserved.
Description
Noncachable
Cachable
CP15
c1 M bit
-
0
1
ARM926EJ-S behavior
ICache disabled. All instruction fetches are fetched from external
memory (AHB).
ICache enabled, MMU disabled. All instruction fetches are
cachable, with no protection checks. All addresses are flat mapped,
that is VA = MVA= PA.
ICache enabled, MMU enabled. Instruction fetches are cachable or
noncachable depending on the page descriptor C bit (see Table 4-2),
and protection checks are performed. All addresses are remapped
from VA to PA, depending on the page entry, that is the VA is
translated to an MVA, and the MVA is remapped to a PA.
ARM926EJ-S behavior
memory.
Cache hit
Cache miss
ICache disabled. All instruction fetches are fetched from external
Table 4-1 CP15 c1 I and M bit settings for the ICache
Table 4-2 Page table C bit settings for the ICache
Read from the ICache.
Linefill from external memory.
Caches and Write Buffer
4-5
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