SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 163
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 163 of 248
- Download datasheet (2Mb)
8.3.1
ARM DDI0198D
Coprocessor pipeline
CPLATECANCEL
Interlocked MCR
CPINSTR[31:0]
CPDOUT[31:0]
CPDIN[31:0]
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
MCR
MRC
CLK
If the data for an MCR operation is not available inside the ARM9EJ-S core pipeline
during its first Decode cycle, then the ARM9EJ-S core pipeline interlocks for one or
more cycles until the data is available. An example of this is where the register being
transferred is the destination from a preceding LDR instruction. In this situation the
MCR instruction enters the Decode stage of the coprocessor pipeline, and remains there
for a number of cycles before entering the Execute stage.
Figure 8-5 shows an example of an interlocked MCR.
MCR/MRC
Copyright © 2001-2003 ARM Limited. All rights reserved.
Fetch
(interlock)
Decode
WAIT
Decode
WAIT
Execute
(WAIT)
LAST
Execute
(LAST)
Ignored
Figure 8-5 Interlocked MCR
Coproc data
Memory
Coprocessor Interface
Write
8-7
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