SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 129
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 129 of 248
- Download datasheet (2Mb)
ARM926EJ-S
5.5.3
ARM DDI0198D
DRADDR[17:0]
DRWD[31:0]
DRWBL[3:0]
DRSIZE[3:0]
DRRD[31:0]
DRWAIT
DRnRW
Multiple banks of RAM example
DRCS
CLK
b0110 DIN[7:0]
The rules for connecting four RAM blocks are:
•
•
In little-endian mode, DRWBL[0] indicates the LSB of the word and DRWBL[3]
indicates the MSB. In big-endian mode, DRWBL[3] indicates the LSB of the word and
DRWBL[0] indicates the MSB.
If you have to create a large memory out of smaller RAM blocks, there are two methods
for doing this:
•
CLK
CS
DRWR[7:0]
32K RAM
Byte 0
A[14:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Each byte-wide RAM has the same address and chip-select control as the
word-wide RAM.
The following connections must be made:
—
—
—
—
If minimizing power consumption is more important than a fast design, you must
follow the example in Optimizing for power on page 5-22.
DOUT[7:0]
Note
DRADDR[14:0]
WE
DRWBL[0], DRWD[7:0], and DRRD[7:0], connect to RAM byte 0
DRWBL[1], DRWD[15:8], and DRRD[15:8], connect to RAM byte 1
DRWBL[2], DRWD[23:16], and DRRD[23:16], connect to RAM byte 2
DRWBL[3], DRWD[31:24], and DRRD[31:24], connect to RAM byte 3.
DRRD[7:0]
DRWBL[0]
DIN[7:0]
CLK
CS
DRWR[15:8]
32K RAM
Byte 1
A[14:0]
DOUT[7:0]
WE
DRRD[15:8]
DRWBL[1]
DIN[7:0]
CLK
CS
Figure 5-13 Byte-banks of RAM example
DRWR[23:16]
32K RAM
Byte 2
A[14:0]
DOUT[7:0]
WE
DRRD[23:16]
DRWBL[2]
Tightly-Coupled Memory Interface
DIN[7:0]
CLK
CS
DRWR[31:24]
32K RAM
Byte 3
A[14:0]
DOUT[7:0]
WE
DRRD[31:24]
DRWBL[3]
5-21
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