SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 56
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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Programmer’s Model
2-28
The format of the Cache Lockdown Register L bits is shown in Table 2-21. All cache
ways are available for allocation from reset.
You can use the cache lockdown and cache unlock procedures described in:
•
•
Specific loading of addresses into a cache way
The procedure to lock down code and data into way i of a cache with N ways using
Format C involves making it impossible to allocate to any cache way other than the
target cache way:
1.
2.
3.
4.
5.
6.
Bits
[31:16]
[15:4]
3
2
1
0
Copyright © 2001-2003 ARM Limited. All rights reserved.
Specific loading of addresses into a cache way
Cache unlock procedure on page 2-29.
Ensure that no processor exceptions can occur during the execution of this
procedure, for example by disabling interrupts. If this is not possible, all code and
data used by any exception handlers must be treated as code and data as in steps
2 and 3.
If an ICache way is being locked down, ensure that all the code executed by the
lockdown procedure is in an uncachable area of memory (including TCM) or in
an already locked cache way.
If a DCache way is being locked down, ensure that all data used by the lockdown
procedure is in an uncachable area of memory (including TCM) or is in an already
locked cache way.
Ensure that the data/instructions that are to be locked down are in a cachable area
of memory.
Ensure that the data/instructions that are to be locked down are not already in the
cache. Use the register c7 clean and/or invalidate operations to ensure this.
Write to register c9, CRm == 0, setting L==0 for bit i and L==1 for all other ways.
This enables allocation to the target cache way.
4-way associative
UNP/SBZP
L bit for Way 3
L bit for Way 2
L bit for Way 1
L bit for Way 0
Notes
Reserved
SBO
Bits[3:0] are the L bits for each cache way:
0 = Allocation to the cache way is determined by the
standard replacement algorithm (reset state)
1 = No allocation is performed to this cache way.
Table 2-21 Cache Lockdown Register L bits
ARM DDI0198D
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