SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 159

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.10
ARM DDI 0029G
Store multiple registers
Register
Single register
n registers (n>1)
The store multiple instruction proceeds very much as load multiple instruction, without
the final cycle. The abort handling is much more straightforward as there is no
wholesale overwriting of registers.
The cycle timings are listed in Table 6-13 where:
•
•
Ra is the first register specified
R• are the subsequent registers specified.
Cycle
1
2
1
2
•
n
n+1
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
alu
pc+3L
pc+8
alu
alu+•
alu+•
alu+•
pc+12
Table 6-13 Store multiple registers instruction cycle operations
MAS[1:0]
i
2
i
2
2
2
2
nRW
0
1
0
1
1
1
1
Data
(pc+2L)
Ra
(pc+2L)
Ra
R•
R•
R•
nMREQ
0
0
0
0
0
0
0
Instruction Cycle Timings
SEQ
0
0
0
1
1
1
0
nOPC
0
1
0
1
1
1
1
6-17