SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 89

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
nENOUT
PAD
DOUT[31:0]
XDATA[31:0]
ARM7TDMI
DIN[31:0]
Figure 3-14 External connection of unidirectional buses
Bidirectional data bus
When BUSEN is LOW, the buffer between DIN[31:0] and D[31:0] is disabled. Any
data presented on DIN[31:0] is ignored. Also, when BUSEN is LOW, the value on
DOUT[31:0] is forced to
.
When the ARM7TDMI processor is reading from memory DIN[31:0] is acting as an
input. During write cycles the ARM7TDMI core must output data. During phase 2 of
the previous cycle, the signal nRW is driven HIGH to indicate a write cycle. During the
actual cycle, nENOUT is driven LOW to indicate that the processor is driving D[31:0]
as an output. Figure 3-15 on page 3-20 shows the bus timing with the data bus enabled.
Figure 3-16 on page 3-20 shows the circuit that exists in the processor for controlling
exactly when the external bus is driven out.
ARM DDI 0029G
Copyright © 1994-2001. All rights reserved.
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