SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 87

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SAM9M11

Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9M11

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
3.6
3.6.1
ARM DDI 0029G
Data timed signals
D[31:0], DOUT[31:0], and DIN[31:0]
This section describes:
The ARM7TDMI processor provides both unidirectional data buses, DIN[31:0],
DOUT[31:0], and a bidirectional data bus, D[31:0]. The configuration input BUSEN is
used to select which is active. Figure 3-11 shows the arrangement of the data buses and
bus-splitter logic.
When the bidirectional data bus is being used then you must disable the unidirectional
buses by driving BUSEN LOW. The timing of the bus for three cycles, load-store-load,
is shown in Figure 3-12 on page 3-18.
D[31:0], DOUT[31:0], and DIN[31:0] on page 3-17
ABORT on page 3-24
Byte latch enables on page 3-24
Byte and halfword accesses on page 3-26.
Copyright © 1994-2001. All rights reserved.
ARM7TDMI
Latch control
EmbeddICE
Buffer control
Logic
Figure 3-11 External bus arrangement
Latch
G
Memory Interface
DIN[31:0]
DOUT[31:0]
D[31:0]
3-17

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