SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 49

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SAM9M11

Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9M11

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
2.2
2.2.1
ARM DDI 0029G
Processor operating states
Switching state
The ARM7TDMI processor has two operating states:
ARM
Thumb
In Thumb state, the Program Counter (PC) uses bit 1 to select between alternate
halfwords.
Transition between ARM and Thumb states does not affect the processor mode or the
register contents.
The operating state of the ARM7TDMI core can be switched between ARM state and
Thumb state using the BX instruction. This is described in the ARM Architecture
Reference Manual.
All exception handling is entered in ARM state. If an exception occurs in Thumb state,
the processor reverts to ARM state. The transition back to Thumb state occurs
automatically on return. An exception handler can change to Thumb state but it must
return to ARM state to allow the exception handler to terminate correctly.
Note
Copyright © 1994-2001. All rights reserved.
32-bit, word-aligned ARM instructions are executed in this state.
16-bit, halfword-aligned Thumb instructions are executed in this state.
Programmer’s Model
2-3

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