SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 266
SAM9M11
Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Specifications of SAM9M11
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.15
B-48
The debug control register
The debug control register is 3 bits wide. Writing control bits occurs during a register
write access with the read/write bit HIGH. Reading control bits occurs during a register
read access with the read/write bit LOW.
Figure B-9 on page B-48 shows the function of each bit in this register.
If Bit 2, INTDIS, is asserted, the interrupt enable signal, IFEN of the core is forced
LOW. Therefore. all interrupts, IRQ and FIQ, are disabled during debugging,
DBGACK is HIGH, or if the INTDIS bit is asserted. The IFEN signal is driven as listed
in Table B-7 on page B-48.
Bits 1 and 0 enable the values on DBGRQ and DBGACK to be forced.
Figure B-11 on page B-51 shows that the value stored in bit 1 of the control register is
synchronized and then ORed with the external DBGRQ before being applied to the
processor. The output of this OR gate is the signal DBGRQI which is brought out
externally from the macrocell.
The synchronization between control bit 1 and DBGRQI is to assist in multiprocessor
environments. The synchronization latch only opens when the TAP controller state
machine is in the RUN-TEST-IDLE state. This enables an enter debug condition to be
set up in all the processors in the system while they are still running. When the condition
is set up in all the processors, it can then be applied to them simultaneously by entering
the RUN-TEST-IDLE state.
Copyright © 1994-2001. All rights reserved.
DBGACK
LOW
HIGH
x
Figure B-9 Debug control register format
INTDIS
2
Table B-7 Interrupt signal control
INTDIS
LOW
x
HIGH
DBGRQ
1
IFEN
HIGH
LOW
LOW
ARM DDI 0029G
DBGACK
Interrupts
Permitted
Inhibited
Inhibited
0
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