SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 130
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 130 of 248
- Download datasheet (2Mb)
Tightly-Coupled Memory Interface
5-22
•
The rules for producing memory out of smaller RAM blocks are:
•
•
•
•
•
•
Optimizing for power
Figure 5-14 on page 5-23 shows how to produce a large memory from two smaller
RAM blocks if you are optimizing for power. Separate chip select control is required
for each RAM block:
CS_bank0 = ~DRADDR[14] & DRCS
CS_bank1 = DRADDR[14] & DRCS
This ensures that only the RAM being accessed is enabled, minimizing power
consumption.
Copyright © 2001-2003 ARM Limited. All rights reserved.
If a fast design is more important than minimizing power consumption, you must
follow the example in Optimizing for speed on page 5-23.
There must be an even number of RAM blocks b (b = 2, 4, 8, for example)
Each RAM block must be the same size.
If the address width of the required memory size is n bits, the address port of the
smaller RAM blocks is m = n-(log
Address bits [m-1:0] are applied to all the RAM blocks.
Address bits [n-1:m] are gated with DRCS for a power optimized solution, or
with IRnRW for a speed optimized solution.
Pipelined address bits [n-1:m] are used to select the correct RAM read data.
b
/log
2
) bits wide.
ARM DDI0198D
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