SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 166

• Manufacturer Part Number: SAM9R64
• Manufacturer: Atmel Corporation

Specifications of SAM9R64

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 49
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 3
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.6
8-10
Busy-waiting and interrupts
Coprocessor pipeline
CPLATECANCEL
CPINSTR[31:0]
The coprocessor is permitted to stall (busy-wait) the processor during the execution of
a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT on CHSDE[1:0]. When the instruction concerned enters the Execute stage
of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles
as required to keep the instruction in the busy-wait loop.
For interrupt latency reasons the coprocessor might be interrupted while busy-waiting,
causing the instruction to be abandoned using CPPASS. The coprocessor must monitor
the state of CPPASS during every busy-wait cycle. If it is HIGH the instruction must be
executed. If it is LOW the instruction must be abandoned.
Figure 8-8 shows a busy-waited coprocessor instruction being abandoned due to an
interrupt.
In Figure 8-8, CPLATECANCEL is also asserted as a result of the Execute
interruption.
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
CLK
Copyright © 2001-2003 ARM Limited. All rights reserved.
CPInstr
Fetch
Decode
WAIT
Execute
(WAIT)
WAIT
Figure 8-8 Busy waiting and interrupts
Execute
(WAIT)
WAIT
Execute
(WAIT)
WAIT
interrupted
ARM DDI0198D
Execute
Ignored