SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 41

• Manufacturer Part Number: SAM9R64
• Manufacturer: Atmel Corporation

Specifications of SAM9R64

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 49
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 3
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
31
All defined control bits are set to zero on reset except the V bit and the B bit. The V bit
is set to zero at reset if the VINITHI signal is LOW, or one if the VINITHI signal is
HIGH. The B bit is set to zero at reset if the BIGENDINIT signal is LOW, or one if the
BIGENDINIT signal is HIGH.
Figure 2-5 shows the format of the Control Register.
Table 2-11 describes the functions of the Control Register bits.
Bit
[31:19]
[18]
[17]
[16]
[15]
[14]
Copyright © 2001-2003 ARM Limited. All rights reserved.
SBZ
Name
-
-
-
-
L4 bit
RR bit
Function
Reserved.
When read returns an Unpredictable value.
When written Should Be Zero, or a value read from bits [31:19] on the
same processor.
Using a read-modify-write sequence when modifying this register
provides the greatest future compatibility.
Reserved, SBO. Read = 1, write = 1.
Reserved, SBZ. Read = 0, write = 0.
Reserved, SBO. Read = 1, write = 1.
Determines if the T bit is set when load instructions change the PC:
0 = loads to PC set the T bit
1 = loads to PC do not set T bit (ARMv4 behavior).
For more details see the ARM Architecture Reference Manual.
Replacement strategy for ICache and DCache:
0 = Random replacement
1 = Round-robin replacement.
19 18 17 16 15 14 13 12 11 10 9 8 7 6
O
S
B
S
B
Z
S
B
O
L
4
Table 2-11 Control bit functions register c1
R
R
V I SBZ R S B
Figure 2-5 Control Register format
Programmer’s Model
SBO
3 2 1 0
C A
M
2-13