SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 155

• Manufacturer Part Number: SAM9R64
• Manufacturer: Atmel Corporation

Specifications of SAM9R64

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 49
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 3
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.1.3
ARM DDI0198D
AHB behavior
This IMB implementation only applies to the ARM926EJ-S processor running code
from a noncachable region of memory. If code is run from a cachable region of memory,
or a different device is used then a different IMB implementation is required. IMBs are
described in Chapter 9 Instruction Memory Barrier.
If instruction prefetching is disabled, all instruction fetches appear on the AHB interface
as single, nonsequential fetches.
If prefetching is enabled then instruction fetches either appear as bursts of four
instructions, or as single, nonsequential fetches. No speculative instruction fetching is
done across a 1KB boundary.
All instruction fetches, including those made in Thumb state, are word transfers (32
bits). In Thumb state a single-word instruction fetch reads two Thumb instructions, and
a four-word burst reads eight instructions.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Noncachable Instruction Fetches
7-3