SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 154
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
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- Download datasheet (2Mb)
Noncachable Instruction Fetches
7.1
7.1.1
7.1.2
7-2
About noncachable instruction fetches
Uses of noncachable code
Self modifying code
The ARM926EJ-S processor performs speculative noncachable instruction fetches to
increase performance. Speculative instruction fetching is enabled at reset. This can be
disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register
c15 on page 2-36). If prefetching is disabled only instruction fetches issued directly by
the ARM9EJ-S core result in instruction fetches on the AHB interface.
The following subsection is divided into:
•
•
•
Although noncachable code performance has been improved compared with other
ARM9 family cached cores, it is still recommended that the ICache is used in
preference, where practical.
Noncachable code has previously been used for boot loaders of operating systems and
for preventing cache pollution. It is worth noting that the ICache can be enabled without
the MMU being enabled (see Chapter 4 Caches and Write Buffer), and that cache
pollution can be controlled using the cache lockdown register (see Cache Lockdown and
TCM Region Registers c9 on page 2-26).
A four-word buffer is used to hold speculatively fetched instructions. Only sequential
instructions are fetched speculatively, and in the event of the ARM9EJ-S core issuing a
nonsequential instruction fetch, the contents of the buffer are discarded (flushed). In
situations where the contents of the prefetch buffer might become invalid during a
sequence of sequential instruction fetches by the ARM9EJ-S core (for example, turning
the MMU on or off, or turning on the ICache), the prefetch buffer is also flushed. This
avoids the requirement for an explicit Instruction Memory Barrier (IMB) operation to
be performed, except when self-modifying code is used. Because the prefetch buffer is
flushed when the ARM9EJ-S core issues a nonsequential instruction fetch, a branch
instruction (or equivalent) can be used to implement the required IMB behavior. This is
illustrated by the following code sequence:
Copyright © 2001-2003 ARM Limited. All rights reserved.
Uses of noncachable code
Self modifying code
AHB behavior on page 7-3.
ARM DDI0198D
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