SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 45
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
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- Download datasheet (2Mb)
2.3.3
2.3.4
ARM DDI0198D
Translation Table Base Register c2
Domain Access Control Register c3
31
Read accesses on the TCM interface are not prevented when an ARM9EJ-S core
memory access is aborted. All reads on the TCM interface must be treated as
speculative. ARM92EJ-S processor write accesses that are aborted do not take place on
the TCM interface.
Register c2 is the Translation Table Base Register (TTBR), for the base address of the
first-level translation table.
Reading from c2 returns the pointer to the currently active first-level translation table in
bits [31:14] and an Unpredictable value in bits [13:0].
Writing to register c2 updates the pointer to the first-level translation table from the
value in bits [31:14] of the written value. Bits [13:0] Should Be Zero.
You can use the following instructions to access the TTBR:
The CRm and Opcode_2 fields Should Be Zero when writing to c2.
Figure 2-6 shows the format of the Translation Table Base Register.
Register c3 is the Domain Access Control Register consisting of 16 two-bit fields as
shown in Figure 2-7 on page 2-18.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Translation table base
14 13
UNP/SBZ
Figure 2-6 TTBR format
Programmer’s Model
0
2-17
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