SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 48
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 48 of 248
- Download datasheet (2Mb)
Programmer’s Model
2.3.7
2.3.8
2-20
Fault Address Register c6
Cache Operations Register c7
Table 2-16 shows the encodings used for the status field in the FSR, and if the Domain
field contains valid information. See Fault address and fault status registers on
page 3-21 for details of MMU aborts.
Register c6 accesses the Fault Address Register (FAR). The FAR contains the Modified
Virtual Address of the access being attempted when a Data Abort occurred. The FAR is
only updated for Data Aborts, not for Prefetch Aborts. The FAR is updated for
alignment faults, and external aborts that occur while the MMU is disabled.
You can use the following instructions to access the FAR:
Writing c6 sets the FAR to the value of the data written. This is useful for a debugger to
restore the value of the FAR to a previous state.
The CRm and Opcode_2 fields Should Be Zero when reading or writing CP15 c6.
Register c7 controls the caches and the write buffer. The function of each cache
operation is selected by the Opcode_2 and CRm fields in the MCR instruction used to
write to CP15 c7. Writing other Opcode_2 or CRm values is Unpredictable.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Priority
Highest
Lowest
Source
Alignment
External abort on translation
Translation
Domain
Permission
External abort
Table 2-16 FSR status field encoding
Size
-
First level
Second level
Section
Page
Section
Page
Section
Page
Section or page
Status
b00x1
b1100
b1110
b0101
b0111
b1001
b1011
b1101
b1111
b10x0
ARM DDI0198D
Domain
Invalid
Invalid
Valid
Invalid
Valid
Valid
Valid
Valid
Valid
Invalid
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