SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 67
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 67 of 248
- Download datasheet (2Mb)
3.1.1
3.1.2
ARM DDI0198D
Access permissions and domains
Translated entries
For large and small pages, access permissions are defined for each subpage (1KB for
small pages, 16KB for large pages). Sections and tiny pages have a single set of access
permissions.
All regions of memory have an associated domain. A domain is the primary access
control mechanism for a region of memory. It defines the conditions necessary for an
access to proceed. The domain determines if:
•
•
•
In the latter two cases, the access permission attributes are ignored.
There are 16 domains. These are configured using the domain access control register
(see Domain Access Control Register c3 on page 2-17).
The main TLB caches 64 translated entries. If, during a memory access, the main TLB
contains a translated entry for the MVA, the MMU reads the protection data to detrmine
if the access is permitted:
•
•
•
If the TLB misses (it does not contain an entry for the MVA) the translation table walk
hardware is invoked to retrieve the translation information from a translation table in
physical memory. When retrieved, the translation information is written into the TLB,
possibly overwriting an existing value.
To enable use of TLB locking features, the location to be written can be specified using
CP15 c10 TLB Lockdown Register.
At reset the MMU is turned off, no address mapping occurs, and all regions are marked
as noncachable and nonbufferable.
Copyright © 2001-2003 ARM Limited. All rights reserved.
access permissions are used to qualify the access
the access is unconditionally allowed to proceed
the access is unconditionally aborted.
if access is permitted and an off-chip access is required, the MMU outputs the
appropriate physical address corresponding to the MVA
if access is permitted and an off-chip access is not required, the cache or TCM
services the access
if access is not permitted, the MMU signals the CPU core to abort.
Memory Management Unit
3-3
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