SAM3N0A Atmel Corporation, SAM3N0A Datasheet - Page 529
SAM3N0A
Manufacturer Part Number
SAM3N0A
Description
Manufacturer
Atmel Corporation
- Current page: 529 of 752
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30.7.1
30.7.1.1
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Baud Rate Generator
Baud Rate in Asynchronous Mode
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate
Generator does not generate any clock. If CD is programmed to 1, the divider is bypassed and
becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 3 times lower than MCK in USART mode, or 6 in SPI
mode.
Figure 30-3. Baud Rate Generator
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi-
ble clock and that OVER is programmed to 1.
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
SCK
Baudrate
Reserved
MCK/DIV
MCK
USCLKS
=
0
1
2
3
--------------------------------------------
(
8 2 Over
SelectedClock
(
–
)CD
16-bit Counter
)
CD
USCLKS = 3
0
SYNC
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
SYNC
SAM3N
SAM3N
SCK
Baud Rate
Sampling
Clock
Clock
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